1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to a serial read/write architecture for dynamic random access memories.
2. Description of the Related Art
With increasing needs for high-speed logic performance of digital systems, high-speed access techniques, which permit high-speed access to data stored in semiconductor memories such as random access memories, are becoming increasingly important. The performance of central processing units, or CPUs is progressing rapidly. Naturally memory accessing requires speeding up accordingly.
To speed up the transfer of necessary data to a CPU, a cache memory is often used as an auxiliary memory of a system main memory formed of a DRAM. In this case, a gate is connected between the CPU and the main memory, and the cache memory is directly connected to the CPU via a data bus and an address bus. A controller is connected to the gate and cache memory so as to control data transfer among the main memory, cache memory and CPU. In this case also, nay, even more particularly in this case, speeding up of data access in the DRAM serving as main memory is very important. This is because, when data that the CPU needs is not accidentally stored in the cache memory (that is, when the data is "mishit"), the gate opens under the control of the controller to fetch necessary data from the main memory. To this end, high-speed accessing of the main memory is essential.
As the presently available data accessing techniques for DRAMs, there are known architectures of the nibble mode, the page mode, the static column mode and so on. However, those architectures cannot successfully meet the above technical requirements. DRAMs themselves are on the path to high-density integration, and the above current data accessing techniques are gradually losing their utility in the midst of rapid increase in integration density of the DRAMs.
More specifically, according to the nibble mode architecture by way of example, data stored in a DRAM are serially accessed with 4 bits or 8 bits as a unit. Column data in a selected row address are accessed in an established order in unit of a predetermined number of bits, thus permitting high-speed read/write. However, idleness will inevitably occur with data transfer between the cache memory and the DRAM because the unit bit number and the accessing order of data units is fixed in a selected row address. In contrast to the nibble mode architecture, according to the page mode or static column mode architecture, although a desired bit can be accessed randomly in a selected row address, an idle time for restoring will inevitably occur in accessing consecutive random bits, which impairs speeding up of data accessing.